Baud (Cerelyze, Inc.)

Frontier AI development is prohibitively expensive today, to the point that only a handful of companies can afford to create it. Baud argues this is because current silicon and software approaches operate orders of magnitude above the theoretical minimum compute required to create and serve the same intelligence, making them wasteful. This waste stems partly from multiplication operations in chips, which scale quadratically with bit width in silicon, unlike addition which scales linearly. As a result, businesses outside a small set of well-resourced players are locked out of owning or advancing their own AI capabilities.

Baud has built an arithmetic representation that losslessly eliminates multiplications and compresses neural networks during both forward and backward passes, paired with an ASIC architecture designed to train and serve this representation more efficiently than incumbent chips at the same process node and memory bandwidth. By trading multiplications for additions, the chip packs more compute and memory into the same die area, making it faster, less power hungry, and simpler to build. To avoid the usual software barrier to ASIC adoption, the team is building a compiler that converts any PyTorch exportable model to their format with bit exact results in most cases, including open source architectures like Qwen, DeepSeek, GLM, Flux, and Wan. They currently have a demo of a small model trained on their ASIC emulated on an FPGA, running inference at over 1000 tokens per second on a single FPGA, and are opening early access to a first cluster supporting pretraining, fine-tuning, RL post-training, and inference.